I'd love to hear from someone who knows more about this than I:
How well do we 'understand' modern chips? I know that computers play a large hand in chip design. How well do the humans who specialize is chip design 'understand' the final product?
I have a little bit of experience with this... I think that almost certainly, no single human understands the whole chip down to the gate level. The complexity is managed by layers of abstraction.
The core architects understand the pipelines, their interactions, and the machine's mechanisms as a whole (e.g. how instruction scheduling happens, how branch mispredict recoveries restore state, etc). But various architects specialize. The people who understand the branch predictors down to the bit level probably don't have the whole instruction scheduler in their heads, and vice versa. And even within an area, architects work with a simulator model (tracks the exact state and mechanisms of the hardware, but typically written in C/C++), so some of the work is "empirical": you'll attempt to change something, run some simulations, and then see some interaction with other mechanisms that you didn't anticipate.
Beyond the architects, the logic designers (the people who actually take the cycle-accurate simulator model and specs, and write RTL, e.g., Verilog) understand every little piece -- every gate, every latch/flop, every state machine -- of their particular units. But it takes a bunch of logic designers to put together a CPU.
This complexity is why there is so much emphasis on verification (pre- and post-silicon) in any CPU project!
I'd love to hear from someone who knows more about this than I:
How well do we 'understand' modern chips? I know that computers play a large hand in chip design. How well do the humans who specialize is chip design 'understand' the final product?
I have a little bit of experience with this... I think that almost certainly, no single human understands the whole chip down to the gate level. The complexity is managed by layers of abstraction.
The core architects understand the pipelines, their interactions, and the machine's mechanisms as a whole (e.g. how instruction scheduling happens, how branch mispredict recoveries restore state, etc). But various architects specialize. The people who understand the branch predictors down to the bit level probably don't have the whole instruction scheduler in their heads, and vice versa. And even within an area, architects work with a simulator model (tracks the exact state and mechanisms of the hardware, but typically written in C/C++), so some of the work is "empirical": you'll attempt to change something, run some simulations, and then see some interaction with other mechanisms that you didn't anticipate.
Beyond the architects, the logic designers (the people who actually take the cycle-accurate simulator model and specs, and write RTL, e.g., Verilog) understand every little piece -- every gate, every latch/flop, every state machine -- of their particular units. But it takes a bunch of logic designers to put together a CPU.
This complexity is why there is so much emphasis on verification (pre- and post-silicon) in any CPU project!