What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against.
It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance with a python interpreter. I guess more testing needs to be done to see if raising the bar is useful.
The same problem exists for x86. Is $program built for x86-64 with SSE2? AVX2? AVX512? (I chose those three because they are programmer-visible. Programmers have to use intrinsics to exploit those ISA extensions effectively.)
For RISC-V the questions to ask are similar: Is this built for RVA20? Or RVA23? (The big feature of RVA23 is the Vector extension, again something that is programmer-visible)
Embedded RISC-V programmers will have to ask a lot more questions. But for most programmers the whole fragmentation thing is simply a giant meme repeated ad nauseam.
People bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores.
On x86 situation is even crazier https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html . Some of the more recent CPUs list ~60 optional features. Even if you look just at generic common profiles you have i386, i486, i586, i686, x86-64, x86-64-v2, x86-64-v3, x86-64-v4. Just a single family of vector instructions has 6 different versions for example: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2. I am not even going to try counting all the variations and optional instructions of AVX512.
On one hand this is an important topic, especially in contexts like which X86-64 profile are the software in Linux distro official repositories targeting.
At the same time no one is bothered by 20 cent ARM mcu not having instructions for atomic memory access, supervisor, SIMD or even floating point.
So if anything RISC-V instruction set optional feature sets are probably better structured and less fragmented (for now) than the current situation with ARM and x86.
I wonder how much this matters for python.
As long as the important dependencies like numpy runtime dispatch RVV, it should probably be fine.
Zba would probably give a small boost. Zbb gives a substantial boost to perf for applications that use clz/popc heavily, but I don't think that would apply to python.
Odd they still have i686-pc-windows-msvc as Tier 1 *. Even Microsoft doesn't have any supported 32bit Windows versions anymore, and C extension modules likely follow Linux (where Python doesn't have any no supported i686 triplets in any tier). It would be more modern to demote its Tier and promote aarch64 Windows or wasm32 instead to Tier 1.
Python's tiering has to do with testability and availability thereof, not modernness. In the case of 32-bit Windows, the reason it's still testable is because Windows still ships a 32-bit userspace, even if Windows itself only supports x86-64.
(From personal experience, testing Windows aarch64 is a massive PITA, even on GitHub Actions, which all common sense would indicate should have the best aarch64 Windows CI runner story.)
Tier1: Windows x64/i686, Linux x64/ARM gcc, Darwin/ARM
Tier2: Linux x64/ARM w/ clang, Windows ARM, WASM, Darwin/x64
Tier3 is a pretty low support level, but tiers 1 and 2 is a pretty short list of major commercial platforms. Also even for developers to fix, availability of e.g. RiscV machines in the cloud to reproduce and fix on is still somewhat limited.
Looks like the most important step towards tier two is mostly about proving the CI infrastructure is reliable (which takes time at tier 3), and have at least two core developers committed to fixing any issues (within 24 hours)
How is Python a dead language due to ML when it's the lingua franca of AI/ML between pytorch, pandas, numpy, langchain, litellm, vLLM, and a whole bunch of other libraries?
What RISC-V extensions is this built for? There is a target triple of riscv64-unknown-linux-gnu listed so i assume the baseline RV64GC that the Linux kernel is built against.
It makes sense to be conservative with a new architecture but new high performance RISC-V cores such as from SiFive[1] are going to meet RVA23. That standard has vector and bit manipulation extensions that could be used to improve performance with a python interpreter. I guess more testing needs to be done to see if raising the bar is useful.
[1]https://www.sifive.com/cores/performance-p800
RISC-V fragmentation bites again...
The same problem exists for x86. Is $program built for x86-64 with SSE2? AVX2? AVX512? (I chose those three because they are programmer-visible. Programmers have to use intrinsics to exploit those ISA extensions effectively.)
For RISC-V the questions to ask are similar: Is this built for RVA20? Or RVA23? (The big feature of RVA23 is the Vector extension, again something that is programmer-visible)
Embedded RISC-V programmers will have to ask a lot more questions. But for most programmers the whole fragmentation thing is simply a giant meme repeated ad nauseam.
People bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores. On x86 situation is even crazier https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html . Some of the more recent CPUs list ~60 optional features. Even if you look just at generic common profiles you have i386, i486, i586, i686, x86-64, x86-64-v2, x86-64-v3, x86-64-v4. Just a single family of vector instructions has 6 different versions for example: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2. I am not even going to try counting all the variations and optional instructions of AVX512.
On one hand this is an important topic, especially in contexts like which X86-64 profile are the software in Linux distro official repositories targeting.
At the same time no one is bothered by 20 cent ARM mcu not having instructions for atomic memory access, supervisor, SIMD or even floating point.
So if anything RISC-V instruction set optional feature sets are probably better structured and less fragmented (for now) than the current situation with ARM and x86.
For AP cores where Python actually runs it’s just “arm8” and pick your incremental version on top.
I wonder how much this matters for python. As long as the important dependencies like numpy runtime dispatch RVV, it should probably be fine.
Zba would probably give a small boost. Zbb gives a substantial boost to perf for applications that use clz/popc heavily, but I don't think that would apply to python.
Odd they still have i686-pc-windows-msvc as Tier 1 *. Even Microsoft doesn't have any supported 32bit Windows versions anymore, and C extension modules likely follow Linux (where Python doesn't have any no supported i686 triplets in any tier). It would be more modern to demote its Tier and promote aarch64 Windows or wasm32 instead to Tier 1.
* https://peps.python.org/pep-0011/#tier-1
Python's tiering has to do with testability and availability thereof, not modernness. In the case of 32-bit Windows, the reason it's still testable is because Windows still ships a 32-bit userspace, even if Windows itself only supports x86-64.
(From personal experience, testing Windows aarch64 is a massive PITA, even on GitHub Actions, which all common sense would indicate should have the best aarch64 Windows CI runner story.)
> RISC-V is now officially supported by CPython as a tier 3 platform!
That's significant, but tier 3 is still a caveat. Still allowed to break without blocking anything or being fixed as a priority.
Sure, but I had to look:
Tier1: Windows x64/i686, Linux x64/ARM gcc, Darwin/ARM
Tier2: Linux x64/ARM w/ clang, Windows ARM, WASM, Darwin/x64
Tier3 is a pretty low support level, but tiers 1 and 2 is a pretty short list of major commercial platforms. Also even for developers to fix, availability of e.g. RiscV machines in the cloud to reproduce and fix on is still somewhat limited.
Windows i686, tier 1, what? I’ll do some digging when I’m home but I feel the sudden need to understand this.
Oh, wow
https://learn.microsoft.com/en-us/lifecycle/products/windows...
Interestingly embedded 32 bit Linux is not tier 1 or 2 though :)
RISC-V is one of those experimental architectures that hardly anyone is actually using, isn't it?
Tier 3, or no support at all, seems an appropriate designation.
Not much on user facing OS, but billions of small controllers
I don't think CPython targets those, though; that seems more like a micropython thing?
Needs to start somewhere.
Looks like the most important step towards tier two is mostly about proving the CI infrastructure is reliable (which takes time at tier 3), and have at least two core developers committed to fixing any issues (within 24 hours)
Atleast CI-class hardware finally exists, with the sifive bigsky
https://www.sifive.com/development-platforms/sifive-bigsky-s...
For quite some times I'm wondering how I could invest in RISC, or RISC related manufacturer but it looks like all companies are private.
Can we do something about CPython Global Interpreter Lock (GIL)?
Free threaded Python - optional but supported
https://docs.python.org/3/howto/free-threading-python.html
I didn't know about that but it feels like Django async support.
Python is a dead language now. The rise with ML now in steep decline. Python is the perfect lang of 2010s.
How is Python a dead language due to ML when it's the lingua franca of AI/ML between pytorch, pandas, numpy, langchain, litellm, vLLM, and a whole bunch of other libraries?
Unison.